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| hc705e5grs/d rev. 1.0 non-disclosure agreement required MC68HC705E5 general release specification february 3, 1997 csic mcu design center austin, texas f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
non-disclosure agreement required general release speci?ation ? motorola, inc., 1997 MC68HC705E5 rev. 1.0 motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release speci?cation list of sections nondisclosure agreement required general release specification MC68HC705E5 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . 17 section 2. memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 section 3. central processing unit (cpu) . . . . . . . . . . . 29 section 4. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 section 5. resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 6. operating modes . . . . . . . . . . . . . . . . . . . . . 47 section 7. input/output (i/o) ports . . . . . . . . . . . . . . . . 51 section 8. timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 section 9. phase-locked loop (pll) synthesis . . . . . . 61 section 10.computer operating properly (cop) watchdog . . . . . . . . . . . 67 section 11. motorola bus (m bus) interface . . . . . . . . . 71 section 12. synchronous serial interface (ssi) . . . . . . 95 section 13. user eprom . . . . . . . . . . . . . . . . . . . . . . . . 107 section 14. instruction set . . . . . . . . . . . . . . . . . . . . . . 115 section 15. electrical specifications . . . . . . . . . . . . . . 133 section 16. mechanical data . . . . . . . . . . . . . . . . . . . 143 section 17. ordering information . . . . . . . . . . . . . . . . 145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections general release specification MC68HC705E5 rev. 1.0 list of sections nondisclosure agreement required f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release speci?cation table of contents nondisclosure agreement required general release specification MC68HC705E5 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2 irq /v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.3 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.5 pa0Cpa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.6 pb0Cpb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.7 pc0Cpc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.8 xfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.9 v ddsyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 section 2. memory 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.6 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents general release specification MC68HC705E5 rev. 1.0 table of contents nondisclosure agreement required section 3. central processing unit (cpu) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.7 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 section 4. interrupts 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . .35 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.5 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.6 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.7 custom periodic interrupt (cpi) . . . . . . . . . . . . . . . . . . . . . . . .39 4.8 synchronous serial interface interrupt (ssi) . . . . . . . . . . . . . .40 4.9 m-bus (i2c) interrupt (m bus) . . . . . . . . . . . . . . . . . . . . . . . . .40 4.10 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.11 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .40 section 5. resets 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.3 external reset ( reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.6 computer operating properly reset (copr). . . . . . . . . . . . . .45 5.6.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.2 cop during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.3 cop during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.4 cop watchdog timer considerations . . . . . . . . . . . . . . . .46 5.7 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC705E5 rev. 1.0 general release speci?cation table of contents nondisclosure agreement required section 6. operating modes 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.5.3 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 section 7. input/output (i/o) ports 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.6 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 section 8. timer 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.3 timer control and status register . . . . . . . . . . . . . . . . . . . . . .57 8.4 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 section 9. phase-locked loop (pll) synthesis 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 9.3 phase-locked loop control register. . . . . . . . . . . . . . . . . . . .63 9.4 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.5 noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents general release specification MC68HC705E5 rev. 1.0 table of contents nondisclosure agreement required section 10. computer operating properly (cop) watchdog 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10.3 system control and status register. . . . . . . . . . . . . . . . . . . . .68 10.4 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.5 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 section 11. motorola bus (m bus) interface 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.3 m-bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.4 m-bus system configuration . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5 m-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5.1 start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.2 slave address transmission. . . . . . . . . . . . . . . . . . . . . . . .75 11.5.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.5.4 repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.5 stop signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.6 arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.7 clock synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 11.5.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 11.6 m-bus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 11.6.1 m-bus address register . . . . . . . . . . . . . . . . . . . . . . . . . . .78 11.6.2 m-bus frequency divider register . . . . . . . . . . . . . . . . . . .80 11.6.3 m-bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 11.6.4 m-bus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 11.6.5 m-bus data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.7 m-bus pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.2 generation of a start signal and the first byte of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.8.3 software responses after transmission or reception of a byte . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.8.4 generation of the stop signal . . . . . . . . . . . . . . . . . . . . . . .91 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC705E5 rev. 1.0 general release speci?cation table of contents nondisclosure agreement required 11.8.5 generation of a repeated start signal . . . . . . . . . . . . . . . .92 11.8.6 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.8.7 arbitration lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.10 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .93 section 12. synchronous serial interface (ssi) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3 ssi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.2 serial data input/output (sdio) . . . . . . . . . . . . . . . . . . . . .98 12.4 ssi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.4.1 ssi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.4.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.4.3 ssi data register (sdr). . . . . . . . . . . . . . . . . . . . . . . . . .104 12.5 ssi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 12.6 ssi during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 12.7 ssi pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 section 13. user eprom 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.4 programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 13.5 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents general release specification MC68HC705E5 rev. 1.0 table of contents nondisclosure agreement required section 14. instruction set 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 14.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 14.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .120 14.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .121 14.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .122 14.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .124 14.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 14.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 section 15. electrical specifications 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .135 15.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .136 15.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15.8 m-bus interface input signal timing. . . . . . . . . . . . . . . . . . . .140 15.9 m-bus interface output signal timing . . . . . . . . . . . . . . . . . .140 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC705E5 rev. 1.0 general release speci?cation table of contents nondisclosure agreement required section 16. mechanical data 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 16.3 28-pin plastic dual-in-line package (case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 16.4 28-pin small outline integrated circuit package (case 751f-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 section 17. ordering information 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 17.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents general release specification MC68HC705E5 rev. 1.0 table of contents nondisclosure agreement required f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release speci?cation list of figures nondisclosure agreement required general release specification MC68HC705E5 list of figures figure title page 1-1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1-2 single-chip mode pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1-3 oscillator connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2-1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2-2 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 3-1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3-2 stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3-3 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3-4 index register (x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3-5 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . .31 3-6 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3-7 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 4-1 interrupt processing flowchart. . . . . . . . . . . . . . . . . . . . . . .37 4-2 stop/wait flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4-3 custom periodic interrupt control and status register (cpicsr) . . . . . . . . . . . . . . . . . . . .39 5-1 reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 5-2 reset and por timing diagram . . . . . . . . . . . . . . . . . . . .43 7-1 port i/o circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 8-1 timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 8-2 timer control and status register (tcsr) . . . . . . . . . . . . .57 8-3 timer counter register (tcr) . . . . . . . . . . . . . . . . . . . . . . .59 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of figures general release specification MC68HC705E5 rev. 1.0 list of figures nondisclosure agreement required figure title page 9-1 pll circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 9-2 phase-locked loop control register (pllcr) . . . . . . . . . .63 10-1 system control and status register (scsr) . . . . . . . . . . . .68 11-1 m-bus transmission signal diagram . . . . . . . . . . . . . . . . . .74 11-2 clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 11-3 m-bus address register (madr) . . . . . . . . . . . . . . . . . . . .78 11-4 m-bus interface block diagram . . . . . . . . . . . . . . . . . . . . . .79 11-5 m-bus frequency divider register (mfdr). . . . . . . . . . . . .80 11-6 m-bus control register (mcr) . . . . . . . . . . . . . . . . . . . . . .82 11-7 m-bus status register (msr) . . . . . . . . . . . . . . . . . . . . . . .84 11-8 m-bus data i/o register (mdr). . . . . . . . . . . . . . . . . . . . . .86 11-9 flowchart of m-bus interrupt routine. . . . . . . . . . . . . . . . . .87 12-1 ssi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 12-2 synchronous serial interface timing (cpol = 1) . . . . . . . .99 12-3 synchronous serial interface timing (cpol = 0) . . . . . . . .99 12-4 ssi control register (scr) . . . . . . . . . . . . . . . . . . . . . . . .100 12-5 ssi status register (ssr) . . . . . . . . . . . . . . . . . . . . . . . . .103 12-6 ssi data register (sdr) . . . . . . . . . . . . . . . . . . . . . . . . . .104 13-1 programmer interface to host . . . . . . . . . . . . . . . . . . . . . .109 13-2 MC68HC705E5 bootloader flowchart . . . . . . . . . . . . . . . .110 13-3 MC68HC705E5 programming circuit . . . . . . . . . . . . . . . .111 13-4 programming register (prog) . . . . . . . . . . . . . . . . . . . . .112 13-5 mask option register (mor) . . . . . . . . . . . . . . . . . . . . . . .113 15-1 maximum supply current versus operating frequency . .137 15-2 typical supply current versus operating frequency. . . . .137 15-3 external interrupt mode diagram . . . . . . . . . . . . . . . . . . . .138 15-4 power-on reset and reset. . . . . . . . . . . . . . . . . . . . . . .139 15-5 m-bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . .141 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release speci?cation list of tables nondisclosure agreement required general release specification MC68HC705E5 list of tables table title page 4-1 vector address for interrupts and reset . . . . . . . . . . . . . . . .34 5-1 cop watchdog timer recommendations . . . . . . . . . . . . . . .46 6-1 operating mode conditions . . . . . . . . . . . . . . . . . . . . . . . . . .47 7-1 i/o pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 8-1 rti rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 9-1 ps1 and ps0 speed selects with 32.768-khz crystal. . . . . .64 10-1 cop rates at fosc = 32.768 khz . . . . . . . . . . . . . . . . . . . . . .69 11-1 m-bus clock prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 12-1 master mode sck frequency select . . . . . . . . . . . . . . . . . .102 13-1 bootloader functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 13-2 cpi rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 13-3 mor read/write based on mode and latch bit . . . . . . . .114 14-1 register/memory instructions. . . . . . . . . . . . . . . . . . . . . . . .120 14-2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . .121 14-3 jump and branch instructions . . . . . . . . . . . . . . . . . . . . . . .123 14-4 bit manipulation instructions. . . . . . . . . . . . . . . . . . . . . . . . .124 14-5 control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of tables general release specification MC68HC705E5 rev. 1.0 list of tables nondisclosure agreement required table title page 14-6 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . .126 14-7 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 17-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification general description non-disclosure agreement required general release specification MC68HC705E5 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.4 mask options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5 functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.1 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.2 irq/v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.3 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.5 pa0Cpa7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.6 pb0Cpb7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.7 pc0Cpc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 1.5.8 xfc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.5.9 v ddsyn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.2 introduction the MC68HC705E5 is a low-cost introduction to the m68hc05 family of microcontrollers (mcus). the hc05 central processing unit (cpu) core has been enhanced with a 15-stage multifunctional timer and programmable phase-locked loop (pll). the mcu is available in a 28-pin package and has two 8-bit input/output (i/o) ports and one 4-bit i/o port. the 8-kbyte memory map consists of user eraseable, programmable read-only memory (eprom), random-access memory (ram), bootloader rom, and i/o. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705E5 rev. 1.0 general description 1.3 features features of the MC68HC705E5 include: ? low cost ? hc05 core ? 28-pin package ? on-chip oscillator (crystal or ceramic resonator) ? phase-locked loop (pll) synthesizer with programmable speed ? synchronous serial interface (ssi) with interrupts and most significant bit (msb) or least significant bit (lsb) first ? m-bus (i 2 c) communication port ? 5120 bytes of user eprom (including 16 bytes of eprom user vectors) ? 384 bytes of on-chip ram ? 15-stage multifunctional timer with programmable input ? real-time interrupt circuit ? computer operating properly (cop) watchdog timer mask option ? custom periodic interrupt circuit ? 20 bidirectional i/o lines ? single-chip mode ? bootloader mode ? power-saving stop and wait modes ? edge-only sensitive or edge- and level-sensitive interrupt trigger mask option ? stop instruction disable mask option ? system control and status register ? illegal address reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description features MC68HC705E5 rev. 1.0 general release specification general description non-disclosure agreement required figure 1-1. block diagram ? 2 accumulator index register stack pointer program counter condition code register osc1 osc2 oscillator internal clock select tpll oscout reset irq/v pp cop cpu m68hc05 cpu alu pc0 pc1 pc2 pc3 v dd v ss cpu registers control port a data direction register port b data direction register pb0 pb1 pb2 pb3/tipl pb4/sck pb5/sdi/sdo pb6/sda pb7/scl pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 port c data direction v ddsyn xfc pll synthesis processor clock timer sram 384 bytes eprom 4608 bytes boot rom 240 bytes custom periodic interrupt system system ssi system i 2 c system register f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705E5 rev. 1.0 general description 1.4 mask options the m68hc705e5 has these four mask options which are handled with five eprom bits (mor). 1. stop instruction (enable/disable) 2. irq (edge-sensitive only or edge- and level-sensitive) 3. cop watchdog timer (enable/disable) 4. cpi rate (1 second, 0.5 second, or 0.25 second) rom versions of this device will have these options programmed by the factory. refer to 13.5 mask option register for additional information . note: a line over a signal name indicates an active low signal. for example, reset is active low. 1.5 functional pin description figure 1-2 shows the single-chip mode pinout for the MC68HC705E5. refer to the following subsections for a description of the pins. figure 1-2. single-chip mode pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 pa2 pa3 pa4 pa5 pa6 pa7 pc0 pc1 pc2 pc3 osc1 osc2 pb7/scl pb6/sda pb4/sck pb3/tipl pb2 pb1 pb0 v dd v ss pb5/sdio xfc v ddsyn pa0 pa1 irq reset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description functional pin description MC68HC705E5 rev. 1.0 general release specification general description non-disclosure agreement required 1.5.1 v dd and v ss power is supplied to the microcontroller using these two pins. v dd is the positive supply and v ss is ground. 1.5.2 irq/v pp this pin is used to supply the eprom with the required programming voltage. in addition, the mask interrupt request has a programmable option that provides two different choices of interrupt triggering sensitivity. the options are: 1. negative edge-sensitive triggering only 2. both negative edge-sensitive and level-sensitive triggering the mcu completes the current instruction before it responds to the interrupt request. when irq/v pp goes low for at least one t ilih , a logic 1 is latched internally to signify an interrupt has been requested. when the mcu completes its current instruction, the interrupt latch is tested. if the interrupt latch contains a logic 1, and the interrupt mask bit (i bit) in the condition code register is clear, the mcu then begins the interrupt sequence. if the option is selected to include level-sensitive triggering, the irq input requires an external resistor to v dd for wired-or operation. the irq/v pp pin contains an internal schmitt trigger as part of its input to improve noise immunity. refer to section 4. interrupts for more detail. note: the voltage on the irq pin affects the mode of operation. for additional information, see section 6. operating modes . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705E5 rev. 1.0 general description 1.5.3 osc1 and osc2 these pins provide control input for an on-chip clock oscillator circuit which can optionally drive a pll clock. a crystal, a ceramic resonator, or an external signal connects to these pins providing a system clock. the oscillator frequency is two times the internal bus rate if the pll is not used. crystal figure 1-3 (a) shows the recommended circuit for using a crystal. the crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. ceramic resonator a ceramic resonator may be used in place of the crystal in cost-sensitive applications. figure 1-3 (a) shows the recommended circuit for using a ceramic resonator. the manufacturer of the particular ceramic resonator being considered should be consulted for specific information. external clock an external clock should be applied to the osc1 input with the osc2 pin not connected (refer to figure 1-3 (b) ). this setup can be used if the user does not wish to run the cpu with a 32.768-khz crystal or the pll frequencies are not suitable for the application. figure 1-3. oscillator connections < osc1 osc2 osc1 osc2 mcu mcu external clock unconnected (a) crystal/ceramic resonator (b) external clock source 330 k w 20 m w 32.768 khz oscillator connections connections 33 pf 10 pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . general description functional pin description MC68HC705E5 rev. 1.0 general release specification general description non-disclosure agreement required 1.5.4 reset this active low pin is used to reset the mcu to a known startup state by pulling reset low. the reset pin contains an internal schmitt trigger as part of its input to improve noise immunity. see section 5. resets for additional information. 1.5.5 pa0Cpa7 these eight i/o lines comprise port a. the state of any pin is software programmable and all port a lines are configured as input during power-on or reset. see 7.6 input/output programming for additional information. 1.5.6 pb0Cpb7 these eight i/o lines comprise port b. the state of any pin is software programmable and all port b lines are configured as input during power-on or reset. pb7 (scl) and pb6 (sda) can be configured as an m-bus interface. (refer to section 11. motorola bus (m bus) interface for m-bus pin configurations). pb3Cpb5 (tipl, sck, and sdio) can be configured as a synchronous serial interface (ssi). refer to section 12. synchronous serial interface (ssi) and to 7.6 input/output programming for additional information. 1.5.7 pc0Cpc3 these four i/o lines comprise port c. the state of any pin is software programmable and all port c lines are configured as input during power-on or reset. 7.6 input/output programming for additional information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general description general release specification MC68HC705E5 rev. 1.0 general description 1.5.8 xfc this pin provides a means for connecting an external filter capacitor to the synthesizer pll filter. for additional information concerning this capacitor, see section 9. phase-locked loop (pll) synthesis . 1.5.9 v ddsyn this pin provides a separate power connection to the pll synthesizer which should be at the same potential as v dd . note: any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the MC68HC705E5 do not require termination, it is recommended to reduce the possibility of static damage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification memory non-disclosure agreement required general release specification MC68HC705E5 section 2. memory 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 eprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.4 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.5 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.6 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 introduction the MC68HC705E5 has an 8-kbyte memory map, consisting of user erasable, programmable read-only memory (eprom), user random access memory (ram), bootloader rom, control registers, and input/output (i/o). refer to figure 2-1 for the memory map and figure 2-2 for the register map. 2.3 eprom the user eprom consists of 5120 bytes of eprom from $0b00 to $1eff and 16 bytes of user vectors from $1ff0 to $1fff. the bootloader rom and vectors are located from $1f01 to $1fef. all of the user vectors, $1ff2 through $1fff, are dedicated to reset and interrupt vectors. location $1f00 is the mask option register (mor). 2.4 ram the user ram, including the stack area, consists of 384 bytes located from $0080 to $01ff. the stack begins at address $00ff. the stack pointer can access 64 bytes of ram from $00ff to $00c0. using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required memory general release specification MC68HC705E5 rev. 1.0 memory 2.5 memory map figure 2-1. memory map i/o 32 bytes unused 96 bytes ram 128 bytes stack 64 bytes ram 256 bytes unused 2304 bytes $0000 $001f $0020 $007f $0080 $00bf $00c0 $00ff $0100 $01ff $0200 $0aff $0b00 port a data register port b data register port c data register unused port a data direction register port b data direction register port c data direction register pll control register timer control & status register timer counter register ssi registers cpi control & status register $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0a-$0c $11 eeprom programming register $12 reset vector (low byte) reset vector (high byte) swi vector (low byte) swi vector (high byte) irq vector (low byte) irq vector (high byte) timer vector (low byte) timer vector (high byte) cpi vector (low byte) cpi vector (high byte) ssi vector (low byte) $1ff0 $1ff5 $1ff6 $1ff7 $1ff8 $1ff9 $1ffa $1ffb $1ffc $1ffd $1ffe unused $1fff scsr register test register $1e $13 $1f ssi vector (high byte) $1ff4 m bus vector (low byte) $1ff3 m bus vector (high byte) $1ff2 unused $1ff1 user eprom 5120 bytes eprom user vectors 16 bytes $1fef $1ff0 $1fff $1eff $1f00 boot rom 240 bytes $1f01 mask option register unused mbus (i 2 c) m bus $18 $1c $1d registers $0d-$10 unused f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory register summary MC68HC705E5 rev. 1.0 general release specification memory non-disclosure agreement required 2.6 register summary addr. register bit 7 6 5 4 3 2 1 bit 0 $0000 port a data register $0001 port b data register $0002 port c data register 0 0 0 0 $0003 unimplemented $0004 port a data direction register $0005 port b data direction register $0006 port c data direction register $0007 pll control register 0 bcs 0 bwc pllon vcotst ps1 ps0 $0008 timer control and status register. tof rtif tofe rtie tofa rtifa rt1 rt0 $0009 timer counter register $000a ssi control register sie se lsbf mstr cpol sdir sr1 sr0 $000b ssi status register sf dcol 0 0 0 0 0 tipl $000c ssi data register d7 d6 d5 d4 d3 d2 d1 d0 $000d unimplemented $000e unimplemented $000f unimplemented $0010 unimplemented $0011 programming register latch 0 epgm $0012 cpi control and status register cpif cpie $0013 system control and status register 0 0 0 stopr iladr copr crs1 crs0 $0014 unimplemented $0015 unimplemented $0016 unimplemented $0017 unimplemented = unimplemented figure 2-2. i/o registers f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required memory general release specification MC68HC705E5 rev. 1.0 memory $0018 m-bus address register mad7 mad6 mad5 mad4 mad3 mad2 mad1 $0019 m bus frequency divider register fd4 fd3 fd2 fd1 fd0 $001a m bus control register men mien msta mtx txak mmux $001b m bus status register mcf maas mbb mal srw mif mxak $001c m bus data i/o register md7 md6 md5 md4 md3 md2 md1 md0 $001d unimplemented $001e unimplemented $001f reserved r r r r r r r r = unimplemented r = reserved addr. register bit 7 6 5 4 3 2 1 bit 0 figure 2-2. i/o registers (continued) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification central processing unit (cpu) non-disclosure agreement required general release specification MC68HC705E5 section 3. central processing unit (cpu) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.3 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.4 index register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 3.5 condition code register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 3.6 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.7 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 3.2 introduction the mcu contains five registers as shown in figure 3-1 . the interrupt stacking order is shown in figure 3-2 . figure 3-1. programming model a 70 x 70 hinzc ccr 11 sp 70 pc 12 0 accumulator index register program counter stack pointer condition code register 0 0 0 0 0 12 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required central processing unit (cpu) general release specification MC68HC705E5 rev. 1.0 central processing unit (cpu) figure 3-2. stacking order 3.3 accumulator the accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. 3.4 index register the index register is an 8-bit register used for the indexed addressing value to create an effective address. the index register may also be used as a temporary storage area. index register pcl accumulator condition code register pch 111 70 stack i n t e r r u p t decreasing unstack r e t u r n increasing note: since the stack pointer decrements during pushes, the pcl is stacked first, followed by pch, etc. pulling from the stack is in the reverse memory addresses memory addresses bit 7 654321 bit 0 a figure 3-3. accumulator (a) bit 7 654321 bit 0 x figure 3-4. index register (x) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . central processing unit (cpu) condition code register MC68HC705E5 rev. 1.0 general release specification central processing unit (cpu) non-disclosure agreement required 3.5 condition code register the ccr is a 5-bit register in which the h, n, z, and c bits are used to indicate the results of the instruction just executed, and the i bit is used to enable interrupts. these bits can be tested individually by a program, and specific actions can be taken as a result of their state. each bit is explained in the following paragraphs. half carry (h) this bit is set during add and adc operations to indicate that a carry occurred between bits 3 and 4. interrupt (i) when this bit is set, the timer and external interrupt are masked (disabled). if an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the i bit is cleared. negative (n) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. zero (z) when set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. carry/borrow (c) when set, this bit indicates that a carry or borrow out of the arithmetic logical unit (alu) occurred during the last arithmetic operation. this bit also is affected during bit test and branch instructions and during shifts and rotates. bit 4 3 2 1 bit 0 hinzc figure 3-5. condition code register (ccr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required central processing unit (cpu) general release specification MC68HC705E5 rev. 1.0 central processing unit (cpu) 3.6 stack pointer the stack pointer contains the address of the next free location on the stack. during an mcu reset or the reset stack pointer (rsp) instruction, the stack pointer is set to location $00ff. the stack pointer then is decremented as data is pushed onto the stack and incremented as data is pulled from the stack. when accessing memory, the seven most significant bits (msb) are permanently set to 0000011. these seven bits are appended to the six least significant register bits to produce an address within the range of $00ff to $00c0. subroutines and interrupts may use up to 64 (decimal) locations. if 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. a subroutine call occupies two locations on the stack; an interrupt uses five locations. 3.7 program counter the program counter is a 13-bit register that contains the address of the next byte to be fetched. note: the hc05 cpu core is capable of addressing 16-bit locations. for this implementation, however, the addressing registers are limited to an 8-kbyte memory map. bit 121110987654321 bit 0 0 00001 sp figure 3-6. stack pointer (sp) bit 121110987654321 bit 0 pc figure 3-7. program counter (pc) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification interrupts non-disclosure agreement required general release specification MC68HC705E5 section 4. interrupts 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.3 hardware controlled interrupt sequence . . . . . . . . . . . . . . . . .35 4.4 software interrupt (swi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.5 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.6 timer interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 4.7 custom periodic interrupt (cpi) . . . . . . . . . . . . . . . . . . . . . . . .39 4.8 synchronous serial interface interrupt (ssi) . . . . . . . . . . . . . .40 4.9 m-bus (i 2 c) interrupt (m bus). . . . . . . . . . . . . . . . . . . . . . . . . .40 4.10 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.11 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.2 introduction the mcu can be interrupted six different ways: the five maskable hardware interrupts ( irq, timer, cpi, ssi, and m bus) and the nonmaskable software interrupt instruction (swi). interrupts cause the processor to save register contents on the stack and to set the interrupt mask (i bit) to prevent additional interrupts. the rti instruction causes the register contents to be recovered from the stack and normal processing to resume. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705E5 rev. 1.0 interrupts unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. the current instruction is the one already fetched and being operated on. when the current instruction is complete, the processor checks all pending hardware interrupts. if interrupts are not masked (ccr i bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. if both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. the swi is executed the same as any other instruction, regardless of the i-bit state. table 4-1. vector address for interrupts and reset register flag name interrupts cpu interrupt vector address n/a n/a reset reset $1ffeC$1fff n/a n/a software swi $1ffcC$1ffd n/a n/a external interrupt irq $1ffaC$1ffb tcsr tof timer over?ow timer $1ff8C$1ff9 n/a rtif real-time interrupt timer $1ff8C$1ff9 cpicsr cpif custom periodic interrupt cpi $1ff6C$1ff7 ssr sf synchronous serial interrupt ssi $1ff4C$1ff5 msr mif m-bus interrupt m bus $1ff2C$1ff3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts hardware controlled interrupt sequence MC68HC705E5 rev. 1.0 general release specification interrupts non-disclosure agreement required 4.3 hardware controlled interrupt sequence the following three functions ( reset, stop, and wait) are not in the strictest sense an interrupt; however, they are acted upon in a similar manner. see figure 4-1 and figure 4-2 . a discussion is provided below. 1. reset a low input on the reset input pin causes the program to vector to its starting address which is specified by the contents of memory locations $1ffe and $1fff. the i bit in the condition code register is also set. much of the mcu is configured to a known state during this type of reset as described in section 5. resets . 2. stop the stop instruction causes the oscillator to be turned off and the processor to sleep until an external interrupt ( irq) or reset occurs. 3. wait the wait instruction causes all processor clocks to stop, but leaves the timer clock running. this rest state of the processor can be cleared by reset, an external interrupt ( irq), or timer interrupt. there are no special wait vectors for these individual interrupts. 4.4 software interrupt (swi) the swi is an executable instruction and a nonmaskable interrupt. it is executed regardless of the state of the i bit in the ccr. if the i bit is zero (interrupts enabled), swi executes after interrupts which were pending when the swi was fetched but before interrupts generated after the swi was fetched. the interrupt service routine address is specified by the contents of memory locations $1ffc and $1ffd. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705E5 rev. 1.0 interrupts 4.5 external interrupt if the i bit of the condition code reister (ccr) is set, all maskable interrupts (internal and external) are disabled. clearing the i bit enables interrupts. the interrupt request is latched immediately following the falling edge of irq. it is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $1ffa and $1ffb. either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger is available as a mask option. note: the internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the i bit is cleared. 4.6 timer interrupt two different timer interrupt flags cause a timer interrupt whenever they are set and enabled. the interrupt flags and enable bits are located in the timer control and status register (tcsr). either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1ff8 and $1ff9. for additional information, refer to 8.3 timer control and status register . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts timer interrupt MC68HC705E5 rev. 1.0 general release specification interrupts non-disclosure agreement required figure 4-1. interrupt processing flowchart from reset external interrupt? irq internal interrupt? timer i bit set? is load pc from: swi: $1ffcC$1ffd irq: $1ffaC$1ffb timer: $1ff8C$1ff9 cpi: $1ff6C$1ff7 ssi: $1ff4C$1ff5 m bus: $1ff2C$1ff3 set i bit. stack pc, x, a, cc clear irq request latch. restore resisters from stack cc, a, x, pc. fetch next instruction. execute instruction. y y y n n n internal interrupt? cpi y n instruction ? swi y n n instruction ? rti y n f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705E5 rev. 1.0 interrupts figure 4-2. stop/wait flowcharts turn on oscillator. wait for time delay to stabilize. 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine restart processor clock. 1. fetch reset vector or 2. service interrupt a. stack b. set i bit c. vector to interrupt routine y y y y y n n n n n stop wait external interrupt ( irq)? reset? oscillator active. timer clock active. processor clocks stopped. stop oscillator and all clocks. clear i bit. timer internal interrupt? cpi, ssi, or m-bus internal interrupt? external interrupt ( irq)? reset? n y y f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . interrupts custom periodic interrupt (cpi) MC68HC705E5 rev. 1.0 general release specification interrupts non-disclosure agreement required 4.7 custom periodic interrupt (cpi) the cpi flag and enable bits are located in the cpi control and status register (cpicsr). a cpi interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $1ff6 and $1ff7. the custom periodic interrupt is mask programmable to a 0.25 second, 0.5 second, or 1 second interrupt. the interrupt is generated from the 32-khz osc1 input by a 15-bit counter. this interrupt is under the control of the custom periodic interrupt control and status register located at $12. cpif custom periodic interrupt flag cpif is a clearable, read-only status bit and is set when the 15-bit counter changes from $7fff to $0000. a cpu interrupt request will be generated if cpie is set. clearing the cpif is done by writing a zero to it. writing a one to cpif has no effect on the bits value. reset clears cpif. cpie custom periodic interrupt enable when this bit is cleared, the cpi interrupts are disabled. when this bit is set, the cpu interrupt request is generated when the cpif bit is set. reset clears this bit. address $0012 bit 7 654321 bit 0 read: 0 cpif 0 cpie 0000 write: reset: 00000000 figure 4-3. custom periodic interrupt control and status register (cpicsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required interrupts general release specification MC68HC705E5 rev. 1.0 interrupts 4.8 synchronous serial interface interrupt (ssi) the ssi flag and enable bits are located in the ssi control (scr) and status (ssr) registers. an ssi interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1ff4 and $1ff5. for additional information, refer to 12.4 ssi registers . 4.9 m-bus (i 2 c) interrupt (m bus) the mif flag and enable bits are located in the m-bus status (msr) and control (mcr) registers. an m-bus interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1ff2 and $1ff3. for further information, refer to 11.6 m-bus registers . 4.10 operation during stop mode the timer system is cleared and the cpi counter is halted when going into stop mode. when stop mode is exited by an external interrupt or an external reset, the internal oscillator will resume, followed by a 4064-cycle internal processor oscillator stabilization delay. the timer system counter is then cleared and operation resumes. the cpi will continue counting once the oscillator resumes and does not wait for the oscillator to stabilize. 4.11 operation during wait mode the cpu clock halts during wait mode, but the timer and cpi remain active. a timer interrupt or custom periodic interrupt, ssi, and m bus will cause the processor to exit wait mode if the interrupts are enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification resets non-disclosure agreement required general release specification MC68HC705E5 section 5. resets 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 5.3 external reset ( reset). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 5.4 internal resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.5 power-on reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.6 computer operating properly reset (copr). . . . . . . . . . . . . .45 5.6.1 resetting the cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.2 cop during wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.3 cop during stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .45 5.6.4 cop watchdog timer considerations . . . . . . . . . . . . . . . .46 5.7 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 5.2 introduction the mcu can be reset from five sources: one external input and four internal restart conditions. the reset pin is an input with a schmitt trigger as shown in figure 5-1 . all the internal peripheral modules will be reset by the internal reset signal (rst). refer to figure 5-2 for reset timing detail. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705E5 rev. 1.0 resets 5.3 external reset ( reset) the reset pin is the only external source of a reset. this pin is connected to a schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. this external reset occurs whenever the reset pin is pulled below the lower threshold and remains in reset until the reset pin rises above the upper threshold. this active-low input will generate the rst signal and reset the cpu and peripherals. the only reset sources that can alter the mcus operating mode are termination of the external reset input or the internal computer operating properly (cop) watchdog reset. note: activation of the rst signal is generally referred to as a reset of the device, unless otherwise specified. figure 5-1. reset block diagram cpu latch reset cop watchdog (copr) rst osc data address ph2 to other peripherals s irq/v tst mode select to irq logic latch r power-on reset (por) v dd illegal address (illaddr) address ph2 clocked one-shot (pulse width = 3 x e-clk) d d disabled stop instruction stopen f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification resets resets external reset (reset) non-disclosure agreement required figure 5-2. reset and por timing diagram pch pcl osc1 2 reset internal processor internal address bus 1 1ffe 1fff v dd v dd threshold (1 to 2 v typical) t vddr 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new pc 1fff notes: 1. internal timing signal and bus information are not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 3 new new op code pcl pch new pc new pc op code new pc clock 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705E5 rev. 1.0 resets the reset pin can also act as an open-drain output. it will be pulled to a low state by an internal pulldown that is activated by any reset source. this reset pulldown device will be asserted only by three to four cycles of the internal clock, ph2 (ph2 period = e clock period), or as long as an internal reset source is asserted. when the external reset pin is asserted, the pulldown device will be turned on for the three to four internal clock cycles only. 5.4 internal resets the four internally generated resets are the initial power-on reset function, the cop watchdog timer reset, the illegal address detector, and the disabled stop instruction. the only reset sources that can alter the mcus operating mode are termination of the external reset input or the internal cop watchdog timer. the other internal resets will not have any effect on the mode of operation when their reset state ends. all internal resets will also assert (pull to logic 0) the external reset pin for the duration of the reset or three to four internal clock cycles, whichever is longer. 5.5 power-on reset (por) the internal por is generated on power-up to allow the clock oscillator to stabilize. the por is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). there is an oscillator stabilization delay of 4064 internal processor clock cycles after the oscillator becomes active. the por will generate the rst signal which will reset the cpu. if any other reset function is active at the end of the 4064-cycle delay, the rst signal will remain in the reset condition until the other reset condition(s) end. por will activate the reset pin pulldown device connected to the pin. v dd must drop below v por for the internal por circuit to detect the next rise of v dd . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets computer operating properly reset (copr) MC68HC705E5 rev. 1.0 general release specification resets non-disclosure agreement required 5.6 computer operating properly reset (copr) the mcu contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. if the cop watchdog timer is allowed to timeout, an internal reset is generated to reset the mcu. regardless of an internal or external reset, the mcu comes out of a cop reset according to the standard rules of mode selection. the cop reset function is enabled or disabled by a mask option and is verified during production testing. the cop watchdog reset will activate the internal pulldown device connected to the reset pin. 5.6.1 resetting the cop preventing a cop reset is done by writing a logic 0 to the copf bit. this action will reset the counter and begin the timeout period again. the copf bit is bit 0 of address $1ff0. a read of address $1ff0 will return user data programmed at that location. 5.6.2 cop during wait mode the cop will continue to operate normally during wait mode. the software should pull the device out of wait mode periodically and reset the cop by writing to the copf bit to prevent a cop reset. 5.6.3 cop during stop mode when the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. the cop counter will be reset when stop mode is entered. if a reset is used to exit stop mode, the cop counter will be held in reset during the 4064 cycles of startup delay. if any operable interrupt is used to exit stop mode, the cop counter will not be reset during the 4064-cycle startup delay and will have that many cycles already counted when control is returned to the program. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required resets general release specification MC68HC705E5 rev. 1.0 resets 5.6.4 cop watchdog timer considerations if enabled by a mask option, the cop watchdog timer is active in all modes of operation (disabled in test and self-check modes). if the cop watchdog timer is selected by a mask option, any execution of the stop instruction (either intentional or inadvertent due to the cpu being disturbed) will cause the oscillator to halt and prevent the cop watchdog timer from timing out. therefore, it is recommended that the stop instruction should be disabled if the cop watchdog timer is enabled. if the cop watchdog timer is selected by a mask option, the cop will reset the mcu when it times out. therefore, it is recommended that the cop watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the cop timeout period. the recommended interactions and considerations for the cop watchdog timer, stop instruction, and wait instruction are summarized in figure 5-1 . 5.7 illegal address reset when an opcode fetch occurs from an address which is not implemented in the ram ($0080C$01ff) or rom ($0f00C$1fff), the part is reset automatically. table 5-1. cop watchdog timer recommendations if the following conditions exist: then the cop watchdog timer should be: stop instruction wait time converted to reset wait time less than cop time-out enable or disable cop by mask option converted to reset wait time more than cop time-out disable cop by mask option acts as stop any length wait time disable cop by mask option f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification operating modes non-disclosure agreement required general release specification MC68HC705E5 section 6. operating modes 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.3 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.4 self-check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.5.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.5.3 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.2 introduction the mcu has two modes of operation: single-chip mode and self-check mode. this section describes these modes as well as the two low-power modes: stop mode and wait mode. refer to table 6-1 for the conditions required to go into each of the operating modes. table 6-1. operating mode conditions reset irq pb1 mode v ss C v dd v ss C v dd single-chip v tst v dd self-check v tst = 2 x v dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required operating modes general release specification MC68HC705E5 rev. 1.0 operating modes 6.3 single-chip mode in single-chip mode, the address and data buses are not available externally, but there are two 8-bit input/output (i/o) ports and one 4-bit i/o port. this mode allows the mcu to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. all address and data activity occurs within the mcu. single-chip mode is entered on the rising edge of reset if the irq pin is within normal operating range. refer to figure 1-2 for the single-chip user mode pinout diagram. 6.4 self-check mode the self-check mode provides an internal check to determine if the device is functional. 6.5 low-power modes the following subsections provide a description of the low-power modes. 6.5.1 stop mode the stop instruction places the mcu in its lowest power-consumption mode. in stop mode, the internal oscillator is turned off, halting all internal processing, including timer (and cop watchdog timer) operation. during stop mode, the i bit in the ccr is cleared to enable external interrupts. all other registers, including the bits in the tcsr, and memory remain unaltered. all input/output lines remain unchanged. the processor can be brought out of stop mode only by an external interrupt or reset. the stop instruction can be disabled by a mask option. when disabled, the stop instruction causes a chip reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . operating modes low-power modes MC68HC705E5 rev. 1.0 general release specification operating modes non-disclosure agreement required refer to figure 4-2 and to 4.10 operation during stop mode for additional information. 6.5.2 wait mode the wait instruction places the mcu in a low power-consumption mode, but the wait mode consumes more power than the stop mode. all cpu action is suspended, but the timer, cpi, cop, ssi, and m bus remain active. an interrupt from the timer, ssi, or m bus can cause the mcu to exit the wait mode. during the wait mode, the i bit in the ccr is cleared to enable interrupts. all other registers, memory, and input/output lines remain in their previous state. the timer, ssi, and/or iic modules may be enabled to allow a periodic exit from the wait mode. refer to figure 4-2 and to 4.11 operation during wait mode for additional information. 6.5.3 data-retention mode the contents of ram and cpu registers are retained at supply voltages as low as 2.0 vdc. this is called the data-retention mode where the data is held, but the device is not guaranteed to operate. reset must be held low during data-retention mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required operating modes general release specification MC68HC705E5 rev. 1.0 operating modes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification input/output (i/o) ports non-disclosure agreement required general release specification MC68HC705E5 section 7. input/output (i/o) ports 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 7.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.6 input/output programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 7.2 introduction in single-chip mode, 20 lines are arranged as two 8-bit input/output (i/o) ports and one 4-bit i/o port. these ports are programmable as either inputs or outputs under software control of the data direction registers. to avoid a glitch on the output pins, write data to the i/o port data register before writing a one to the corresponding data direction register (ddr). 7.3 port a port a is an 8-bit bidirectional port which does not share any of its pins with other subsystems. the port a data register is at $0000 and the ddr is at $0004. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required input/output (i/o) ports general release specification MC68HC705E5 rev. 1.0 input/output (i/o) ports 7.4 port b port b is an 8-bit bidirectional port which does share some of its pins with other subsystems. the address of the port b data register is $0001 and the ddr is at address $0005. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. refer to section 11. motorola bus (m bus) interface and section 12. synchronous serial interface (ssi) for descriptions of port b behavior while either module is enabled. 7.5 port c port c is a 4-bit bidirectional port which does not share any of its pins with other subsystems. the port c data register is at $0002 and the ddr is at $0006. reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. writing a one to a ddr bit sets the corresponding port bit to output mode. 7.6 input/output programming ports a, b, and c may be programmed as inputs or outputs under software control. the direction of the pins is determined by the state of the corresponding bit in the port ddr with each port having an associated ddr. any port a, port b, or port c pin is configured as an output if its corresponding ddr bit is set to a logic 1. a pin is configured as an input if its corresponding ddr bit is cleared to a logic 0. at power-on or reset, all ddrs are cleared, which configures all port a, b, and c pins as inputs. the data direction registers are capable of being written to or read from by the processor. during the programmed output state, a read of the data register actually reads the value of the output data latch and not the i/o pin. see table 7-1 and figure 7-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . input/output (i/o) ports input/output programming MC68HC705E5 rev. 1.0 general release specification input/output (i/o) ports non-disclosure agreement required figure 7-1. port i/o circuitry table 7-1. i/o pin functions r/ w ddr i/o pin function 00 the i/o pin is in input mode. data is written into the output data latch. 01 data is written into the output data latch and output of the i/o pin. 1 0 the state of the i/o pin is read. 11 the i/o pin is in an output mode. the output data latch is read. data direction register bit latched output data bit i/o pin input register bit input i/o output internal hc05 connections f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required input/output (i/o) ports general release specification MC68HC705E5 rev. 1.0 input/output (i/o) ports f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification timer non-disclosure agreement required general release specification MC68HC705E5 section 8. timer 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 8.3 timer control and status register . . . . . . . . . . . . . . . . . . . . . .57 8.4 timer counter register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 8.2 introduction the timer for this device is a 15-stage multifunctional ripple counter. the features include timer overflow, power-on reset (por), and real-time interrupt. as seen in figure 8-1 , the timer is driven by the output of the clock select circuit (as determined by the value of bcs in the pllcr) and then a fixed divide-by-four prescaler. this signal drives an 8-bit ripple counter. the value of this 8-bit ripple counter can be read by the cpu at any time by accessing the timer counter register (tcr) at address $09. a timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of f op /1024. two additional stages produce the por function at f op /4064. this circuit is followed by two more stages, with the resulting clock (f op /16,384) driving the real-time interrupt circuit. the rti circuit consists of three divider stages with a one-of-four selector. the rti rate selector bit and the rti and tof enable bits and flags are located in the timer control and status register at location $0008. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required timer general release specification MC68HC705E5 rev. 1.0 timer figure 8-1. timer block diagram mc68hc05e4 internal bus $09 tcr 7-bit counter interrupt circuit $08 tcsr rti select circuit overflow circuit detect to interrupt logic 8 8 f op f op /2 2 f op /2 10 por tcbp tcsr tcr internal processor clock tof rtif tofe rtie rt1 rt0 rtifa tofa timer control & status register timer counter register (tcr) ? 4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer timer control and status register MC68HC705E5 rev. 1.0 general release specification timer non-disclosure agreement required 8.3 timer control and status register the timer control and status register (tcsr) contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. figure 8-2 shows the value of each bit in the tcsr when coming out of reset. tof timer over flow tof is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $ff to $00. a cpu interrupt request will be generated if tofe is set. clearing the tof is done by writing a logic 1 to tofa. this is a read-only bit. reset also clears tof. rtif real-time interrupt flag the real-time interrupt circuit consists of a 3-stage divider and a one-of-four selector. the clock frequency that drives the rti circuit is f op /2 13 (or f op /8192) with three additional divider stages giving a maximum interrupt period of four seconds at a crystal frequency of 32.768 khz. rtif is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. a cpu interrupt request will be generated if rtie is set. clearing the rtif is done by writing a logic 1 to rtifa. reset also clears rtif. tofe timer overflow enable when this bit is set, a cpu interrupt request is generated when the tof bit is set. reset clears this bit. address: $0008 bit 7 654321 bit 0 read: tof rtif tofe rtie tofa rtifa rt1 rt0 write: reset: 00000011 figure 8-2. timer control and status register (tcsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required timer general release specification MC68HC705E5 rev. 1.0 timer rtie real-time interrupt enable when this bit is set, a cpu interrupt request is generated when the rtif bit is set. reset clears this bit. tofa timer over flow flag acknowledge when a one is written to this bit location, the tof flag bit is cleared. this bit always reads as a zero. rtifa real-time interrupt flag acknowledge when a one is written to this bit location, the rtif flag bit is cleared. this bit always reads as a zero. rt1Crt0 real-time interrupt rate select these two bits select one of four taps from the real-time interrupt circuit. table 8-1 shows the available interrupt rates with several f op values. reset sets rt0 and rt1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. care should be taken when altering rt0 and rt1 if the time-out period is imminent or uncertain. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. table 8-1. rti rates rt1Crt0 rt1 rates at f op frequency specified 16.384 khz 524 khz 1.049 mhz 2.097 mhz 4.194 mhz f op 00 1 s 31.3 ms 15.6 ms 7.8 ms 3.9 ms 2 14 ? f op 01 2 s 62.5 ms 31.3 ms 15.6 ms 7.8 ms 2 15 ? f op 10 4 s 125 ms 62.5 ms 31.3 ms 15.6 ms 2 16 ? f op 11 8 s 250 ms 125.1 ms 62.5 ms 31.3 ms 2 17 ? f op f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . timer timer counter register MC68HC705E5 rev. 1.0 general release specification timer non-disclosure agreement required 8.4 timer counter register the timer counter register (tcr) is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. this counter is clocked at f op divided by four and can be used for various functions including a software input capture. extended time periods can be attained using the tof function to increment a temporary ram storage location, thereby simulating a 16-bit (or more) counter. the power-on cycle clears the entire counter chain and begins clocking the counter. after 4064 cycles, the power-on reset circuit is released, which again clears the counter chain and allows the device to come out of reset. at this point, if reset is not asserted, the timer will start counting up from zero and normal device operation will begin. when reset is asserted any time during operation other than por, the counter chain will be cleared. address: $0009 bit 7 654321 bit 0 read: write: reset: 00000011 = unimplemented figure 8-3. timer counter register (tcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required timer general release specification MC68HC705E5 rev. 1.0 timer f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification phase-locked loop (pll) synthesis non-disclosure agreement required general release specification MC68HC705E5 section 9. phase-locked loop (pll) synthesis 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 9.3 phase-locked loop control register. . . . . . . . . . . . . . . . . . . .63 9.4 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.5 noise immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 9.2 introduction the pll consists of a variable bandwidth loop filter, a voltage-controlled oscillator (vco), a feedback frequency divider, and a digital phase detector. the pll requires an external loop filter capacitor (typically 0.1 m f) connected between xfc and v ddsyn . this capacitor should be located as close to the chip as possible to minimize noise. v ddsyn is the supply source for the pll and should be bypassed to minimize noise. the v ddsyn bypass cap should be as close as possible to the chip. the phase detector compares the frequency and phase of the feedback frequency (t fb ) and the crystal oscillator reference frequency (t ref ) and generates the output, pcomp, as shown in figure 9-1 . the output waveform is then integrated and amplified. the resultant dc voltage is applied to the voltage controlled oscillator. the output of the vco is divided by a variable frequency divider of 256, 128, 64, or 32 to provide the feedback frequency for the phase detector. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required phase-locked loop (pll) synthesis general release specification MC68HC705E5 rev. 1.0 phase-locked loop (pll) synthesis figure 9-1. pll circuit to change pll frequencies, follow the procedure outlined here: 1. clear bcs to enable the low-frequency bus rate. 2. clear pllon to disable the pll and select high bandwidth. 3. select the speed using ps1 and ps0. 4. set pllon to enable the pll. 5. wait a time of 90% t plls for the pll frequency to stabilize and select manual low bandwidth, wait another 10% t plls . 6. set bcs to switch to the high-frequency bus rate the user cannot switch among the high speeds with the bcs bit set. following the procedure above will prevent possible bursts of high-frequency operation during the re-configuration of the pll. whenever the pll is first enabled, the wide bandwidth mode should be used. this enables the pll frequency to ramp up quickly. when the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth mode to make the final frequency more stable. loop filter vco phase pcomp pllout frequency divider osc1 xfc crystal oscillator ps1 ps0 to clock detect generation circuitry clock select bcs 0.1 m f 0.1 m f v ddsyn t ref t fb ? 2 osc1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . phase-locked loop (pll) synthesis phase-locked loop control register MC68HC705E5 rev. 1.0 general release specification phase-locked loop (pll) synthesis non-disclosure agreement required 9.3 phase-locked loop control register this read/write register contains the control bits which select the pll frequency and enable/disable the synthesizer. bcs bus clock select when this bit is set, the output of the pll is used to generate the internal processor clock. when clear, the internal bus clock is driven by the crystal (osc1 ? 2). once bcs has been changed, it may take up to 1.5 osc1 cycles + 1.5 pllout cycles to make the transition. during the transition, the clock select output will be held low and all cpu and timer activity will cease until the transition is complete. before setting bcs, allow at least a time of t plls after pllon is set. this bit cannot be set unless the pllon bit is already set on a previous instruction. reset clears this bit. bwc bandwidth control this bit selects high bandwidth control when set and low bandwidth control when clear. the low bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on or off. when the pll is turned on, the bwc bit should be set to a logic 1 for a time of 90% t plls to allow the pll time to acquire a frequency close to the desired frequency. the bwc bit should then be cleared and software should delay for a time 10% t plls to allow the pll time to make the final adjustments. the pll clock cannot be used (bcs bit set). although it is not prohibited in hardware, the bcs bit should not be set unless the bwc bit is cleared and the proper delay times have been followed. the pll will generate a lower jitter clock when the bwc bit is cleared. reset clears this bit. address: $0007 bit 7 654321 bit 0 read: 0 bcs 0 bwc pllon vcotst ps1 ps0 write: reset: 00001101 figure 9-2. phase-locked loop control register (pllcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required phase-locked loop (pll) synthesis general release specification MC68HC705E5 rev. 1.0 phase-locked loop (pll) synthesis pllon pll on this bit activates the synthesizer circuit without connecting it to the control circuit. this allows the synthesizer to stabilize before it can drive the cpu clocks. when this bit is cleared, the pll is shut off and the bcs bit cannot be set. (setting the bcs bit would engage the disabled pll onto the bus.) reset sets this bit. note: pllon cannot be cleared unless the bcs bit has been cleared on a previous write to the register. vcotst vco test this bit is used to isolate the loop filter from the vco to facilitate testing. when cleared only in test or self-check modes, the low bandwidth mode of the pll filter is disabled. when set, the loop filter operates as indicated by the value of the bwc bit. reset sets this bit. note: this bit is intended for use by motorola to test and characterize the pll. this bit cannot be cleared in user mode. ps1Cps0 pll synthesizer speed select these two bits select one-of-four taps from the pll to drive the cpu clocks. these bits are used in conjunction with pllon and bcs bits in the pll control register. these bits should not be written if bcs in the pllcr is at a logic high. reset clears ps1 and sets ps0, choosing a bus clock frequency of 1.049 mhz. table 9-1. ps1 and ps0 speed selects with 32.768-khz crystal ps1Cps0 cpu bus clock frequency (f op ) 0 0 524 khz 0 1 1.049 mhz reset condition 1 0 2.097 mhz see note below 1 1 4.194 mhz see note below note: for the standard MC68HC705E5, the 4.194-mhz bus clock frequency should nev- er be selected, and the 2.097-mhz bus clock frequency should not be selected when running the part below v dd = 4.5 v. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . phase-locked loop (pll) synthesis operation during stop mode MC68HC705E5 rev. 1.0 general release specification phase-locked loop (pll) synthesis non-disclosure agreement required 9.4 operation during stop mode the pll is switched to low-frequency bus rate and is temporarily turned off when stop is executed. coming out of stop mode with an external irq, the pll is turned on with the same configuration it had before going into stop, with the exception of bcs which is reset. otherwise, the pll control register is in the reset condition. 9.5 noise immunity the mcu should be insulated as much as possible from noise in the system. we recommend the following steps be taken to help prevent problems due to noise injection. 1. the application environment should be designed so that the mcu is not near signal traces which switch often, such as a clock signal. 2. the oscillator circuit for the mcu should be placed as close as possible to the osc1 and osc2 pins on the mcu. 3. all power pins should be filtered (to minimize noise on these signals) by using bypass capacitors placed as close as possible to the mcu. see the application note designing for electromagnetic compatibility (emc) with hcmos microcontrollers available through the motorola literature distribution center, motorola document number an1050/d. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required phase-locked loop (pll) synthesis general release specification MC68HC705E5 rev. 1.0 phase-locked loop (pll) synthesis f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification computer operating properly (cop) watchdog non-disclosure agreement required general release specification MC68HC705E5 section 10. computer operating properly (cop) watchdog 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 10.3 system control and status register. . . . . . . . . . . . . . . . . . . . .68 10.4 cop during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.5 cop during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 10.2 introduction the cop watchdog system is a mask-programmable feature which will generate a system reset if not serviced within the specified cop timeout period. the cop counter chain is derived from an output of the cpi circuit. this input signal is divided to give the cop reset rate selected by the first write to the system control and status register (scsr) located at address $13. a cop reset is done by writing a logic 0 to bit zero of address $1ff0. this will reset the cop counter chain and begin the timeout countdown again. the cop counter chain is also cleared when the mcu is in reset or stop mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required computer operating properly (cop) watchdog general release specification MC68HC705E5 rev. 1.0 computer operating properly (cop) watchdog 10.3 system control and status register the scsr is a read/write register containing the control flags for the cop rate, cop inhibit, and irq level and status flags indicating the cause of the last reset. figure 10-1 shows the value of each bit in the scsr when coming out of reset. note: the debounce time for the irq input must be shorter than the cop timeout period. stopr illegal stop instruction reset stopr is a read-only status bit. this bit is set by the execution of a stop instruction when the stop instruction option is disabled. this bit is cleared by por, external reset, or cop reset. 1 = last reset was the execution of a disabled stop instruction. 0 = last reset was not the execution of a disabled stop instruction. iladr illegal address reset iladr is a read-only status bit. this bit is set by an iladr reset, but is cleared by por, external reset, or cop reset. 1 = last reset was an iladr reset. 0 = last reset was not an iladr reset. address: $0013 bit 7 654321 bit 0 read: 0 0 0 stopr iladr copr crs1 crs0 write: reset: 0 0 0 r r r 0 0 r = determined by cause of previous reset figure 10-1. system control and status register (scsr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . computer operating properly (cop) watchdog system control and status register MC68HC705E5 rev. 1.0 general release specification computer operating properly (cop) watchdog non-disclosure agreement required copr cop reset copr is a read-only status bit. this bit is set by a cop reset, but is cleared by por, external reset, or illegal address reset. 1 = last reset was a cop reset. 0 = last reset was not a cop reset. note: the cop watchdog reset is a mask option. therefore, a cop reset will only occur when this option is enabled. this option cannot be disabled by software. crs1 and crs0 cop rate select the value of these two bits determines the cop timeout rate. these bits can be written only on the first write to this register after reset. if these bits are never written to, the cop reset rate will be set at one second. the cop counter chain is cleared when these bits are written. note: although these bits default to zero, the user should write to these bits to prevent subsequent writes from changing the cop rate. a bit set/clear for any bit in this register is executed as a read-modify-write of this register. if used as the first write to this register, further writes to crs1 and crs0 would not be valid, and the default value would be set. table 10-1. cop rates at f osc = 32.768 khz crs1 crs0 minimum cop rate 0 0 1 second 0 1 2 seconds 1 0 4 seconds 1 1 8 seconds f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required computer operating properly (cop) watchdog general release specification MC68HC705E5 rev. 1.0 computer operating properly (cop) watchdog 10.4 cop during wait mode the cpu clock halts during wait mode, but the oscillator and the cop system are still active. the software should exit wait mode to service the cop system before the cop timeout period. 10.5 cop during stop mode prior to entry into stop mode, the cop should be cleared. this allows for proper stop recovery and eliminates a possible cop time-out during stop mode recovery, if the cop was about to time out prior to the stop instruction. if enabled, stop mode turns off the oscillator and, therefore, will stop the cop. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required general release specification MC68HC705E5 section 11. motorola bus (m bus) interface 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.3 m-bus interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.4 m-bus system configuration . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5 m-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5.1 start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.2 slave address transmission. . . . . . . . . . . . . . . . . . . . . . . .75 11.5.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.5.4 repeated start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.5 stop signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.6 arbitration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.5.7 clock synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 11.5.8 handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 11.6 m-bus registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 11.6.1 m-bus address register . . . . . . . . . . . . . . . . . . . . . . . . . . .78 11.6.2 m-bus frequency divider register . . . . . . . . . . . . . . . . . . .80 11.6.3 m-bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 11.6.4 m-bus status register . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 11.6.5 m-bus data i/o register . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.7 m-bus pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.2 generation of a start signal and the first byte of data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 11.8.3 software responses after transmission or reception of a byte . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.8.4 generation of the stop signal . . . . . . . . . . . . . . . . . . . . . . .91 11.8.5 generation of a repeated start signal . . . . . . . . . . . . . . . .92 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.8.6 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.8.7 arbitration lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 11.9 operation during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.10 operation during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .93 11.2 introduction motorola bus (m bus) is a 2-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. it is fully compatible to i 2 c bus standards and is similar to the mc68hc05t10. this bus is suitable for applications that require frequent communications over a short distance between a number of devices. it also provides a flexibility that allows additional devices to be connected to the bus. the maximum data rate is limited to 100 kbits and the maximum communication distance and number of devices that can be connected is limited by the maximum bus capacitance of 400 pf. the m-bus system is a true multimaster bus including collision detection and arbitration to prevent data corruption if two or more masters intend to control the bus simultaneously. this feature provides the capability for complex applications with multiprocessor control. it may also be used for rapid testing and alignment of end products by way of external connections to an assembly-line computer. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus interface features MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required 11.3 m-bus interface features features of the m-bus interface include: ? fully compatible with i 2 c bus standard ? multimaster operation ? software programmable for 1of 32 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost driven interrupt with automatic mode switching from master to slave ? calling address identification interrupt ? generate/detect the start or stop signal ? repeated start signal generation ? generate/recognize the acknowledge bit ? bus busy detection 11.4 m-bus system configuration the m-bus system uses a serial data line (sda) and a serial clock line (scl) for data transfer. all devices connected to it must have open-drain or open-collector outputs and the logical and function is performed on both lines by two pullup resistors. 11.5 m-bus protocol normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer, and stop signal. these are described briefly in the following subsections and illustrated in figure 11-1 . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.5.1 start signal when the bus is free (for example, no master device is engaging the bus and both scl and sda lines are at logical high), a master may initiate communication by sending a start signal. as shown in figure 11-1 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. figure 11-1. m-bus transmission signal diagram 100 101 01 0 10 111 00 no acknowledge msb msb lsb sda scl start signal stop signal lsb acknowledge bit 100 101 01 0 10 111 00 no acknowledge msb msb lsb sda scl start signal stop signal lsb acknowledge bit repeated start signal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus protocol MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required 11.5.2 slave address transmission immediately after the start signal, the first byte of data transfer is the slave address transmitted by the master. this data is a 7-bit calling address followed by a r/ w bit. the r/ w bit tells the slave the desired direction of data transfer. only the slave with a matched address will respond by sending back an acknowledge bit. this acknowledge bit is accomplished by pulling sda low on the ninth clock cycle. (see figure 11-1 .) 11.5.3 data transfer once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction specified by the r/ w bit sent by the calling master. each data byte is eight bits long. data can be changed only when scl is low and must be held stable while scl is high as shown in figure 11-1 . the msb is transmitted first and each byte has to be followed by an acknowledge bit. the acknowledge bit is signalled by the receiving device by pulling the sda low on the ninth clock cycle. therefore, one complete data byte transfer needs nine clock cycles. if the slave receiver does not acknowledge the master, the sda line should be left high by the slave. the master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new transfer. if the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it means an end of data to the slave. the slave should now release the sda line for the master to generate a stop or start signal. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.5.4 repeated start signal as shown in figure 11-1 , a repeated start signal is used to generate a start signal without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 11.5.5 stop signal the master can terminate the communication by generating a stop signal to free the bus. however, the master may generate a start signal followed by a calling command without first generating a stop signal. this is called repeat start. a stop signal is defined as a low-to-high transition of sda while scl is at logical high. (see figure 11-1 .) 11.5.6 arbitration procedure this interface circuit is a true multimaster system which allows more than one master to be connected to it. if two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. a data arbitration procedure determines the priority. the masters will lose arbitration if they transmit a logic 1 while another transmits logic 0. the losing masters will immediately switch over to slave receive mode and stop its data and clock outputs. in this case, the transition from master to slave mode will not generate a stop condition; however, a software bit will be set by hardware to indicate loss of arbitration. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus protocol MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required 11.5.7 clock synchronization since wired-and logic is performed on the scl line, a high-to-low transition will affect the devices connected to the bus. the devices start counting their low period and once a device's clock has gone low, it will hold the scl line low until the clock high state is reached. however, the change of low to high in this device clock may not change the state of the scl line if another device clock is still within its low period. therefore, the synchronized clock scl will be held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time. (see figure 11-2 .) when all devices concerned have counted off their low period, the synchronized scl line will be released and go high. there will then be no difference between the device clocks and the state of the scl line and all devices will start counting their high periods. the first device to complete its high period will again pull the scl line low. 11.5.8 handshaking the clock synchronization mechanism can be used as a handshake in data transfer. slave devices may hold the scl low after completion of one byte. in such cases, the device will halt the bus clock and force the master clock into a wait state until the slave releases the scl line. figure 11-2. clock synchronization scl scl2 scl1 internal counter reset wait start counting high period f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.6 m-bus registers five different registers are used in the m-bus interface. the internal configuration of these registers is discussed in the following paragraphs. note: the register addresses show only the low-order address bits (for example abl3Cabl0). the registers can be placed anywhere in the device memory map by generating an appropriate module select signal in the map logic. a block diagram of the m-bus system is shown in figure 11-3 . 11.6.1 m-bus address register bit 1Cbit 7 each of these bits contains its own specific slave address. this register is cleared upon reset. address: $0018 bit 7 654321 bit 0 read: mad7 mad6 mad5 mad4 mad3 mad2 mad1 write: reset: 0000000 = unimplemented figure 11-3. m-bus address register (madr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface motorola bus (m bus) interface m-bus registers non-disclosure agreement required figure 11-4. m-bus interface block diagram m i e n m s t a m t x t x a k m e n m a a s m b b m a l s r w m c f m i f r x a k address register transmitter shift register frequency divider register address comparator receiver control transmitter control control register status register m-bus interrupt start, stop detector & arbitration start, stop generator & timing sync m-bus clock generator sync logic scl control sda control scl interrupt data bus receiver shift register sda f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.6.2 m-bus frequency divider register bit 0Cbit 4 these bits are used for clock rate selection. the serial bit clock frequency is equal to the cpu clock divided by the divider shown in table 11-1 . this register is cleared upon reset. for a 4-mhz external crystal operation (2-mhz internal operating frequency), the serial bit clock frequency of the m-bus ranges from 460 hz to 90,909 hz. address: $0019 bit 7 654321 bit 0 read: fd4 fd3 fd2 fd1 fd0 write: reset: 0 0000 = unimplemented figure 11-5. m-bus frequency divider register (mfdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus registers MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required table 11-1. m-bus clock prescaler fd4, fd3, fd2, fd1, fd0 divider fd4, fd3, fd2, fd1, fd0 divider 00000 22 10000 352 00001 24 10001 384 00010 28 10010 448 00011 34 10011 544 00100 44 10100 704 00101 48 10101 768 00110 56 10110 896 00111 68 10111 1088 01000 88 11000 1408 01001 96 11001 1536 01010 112 11010 1792 01011 136 11011 2176 01100 176 11100 2816 01101 192 11101 3072 01110 224 11110 3584 01111 272 11111 4352 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.6.3 m-bus control register the m-bus control register (mcr) provides five control bits and is cleared upon reset. men m-bus enable bit if men is set, the m-bus interface system is enabled. if men is cleared, the interface is reset and disabled. the men bit must be set first before any bits of mcr are set. mien m-bus interrupt enable bit if mien is set, an interrupt occurs provided the mif flag in the status register is set and the i bit in the condition code register is cleared. if mien is cleared, the m-bus interrupt is disabled. msta master/slave mode select bit upon reset, this bit is cleared. when this bit is changed from a logic 0 to a logic 1, a start signal is generated on the bus, and master mode is selected. when this bit is changed from a logic 1 to a logic 0, a stop signal is generated and the operating mode changes from master to slave. in master mode, a bit clear immediately followed by a bit set generates a repeated start signal (see figure 11-1 ) without generating a stop signal. 1 = master 0 = slave address: $001a bit 7 654321 bit 0 read: men mien msta mtx txak mmux write: reset: 000000 = unimplemented figure 11-6. m-bus control register (mcr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus registers MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required mtx transmit/receiver mode select bit this bit selects the direction of master and slave transfers. when addressed as a slave, this bit should be set by software according to the srw bit in the status register. in master mode, this bit should be set according to the type of transfer required. hence, for address cycles this bit will always be high. 1 = transmit 0 = receive txak transmit acknowledge enable bit if txak is cleared, an acknowledge signal will be sent out to the bus at the ninth clock bit after receiving one byte of data. when txak is set, there will be no acknowledge signal response (for example, acknowledge bit = 1). mmux m-bus multiplexer this bit is used to enable pb7 and pb6 to be under the control of the m-bus circuit. when set, both pb7 and pb6 become open-collector outputs or inputs when enabled by the m-bus control. when cleared pb7 and pb6 are under control of the port ddr logic. this bit can be set or cleared independent of the men bit. caution should be used if pb7 and pb6 are used as general-purpose i/o. 1 = m-bus control 0 = por condition, port b ddr control f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.6.4 m-bus status register this status register is software readable only with exception of bit 1 (mif) and bit 4 (mal) which are software clearable. all bits are cleared upon reset except bit 7 (mcf) and bit 0 (rxak). mcf data transferring bit while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the ninth clock of a byte transfer. 1 = transfer complete 0 = transfer in progress maas addressed as a slave bit when its own specific address (madr) is matched with the calling address, this bit is set. the cpu is interrupted provided mien is set. then cpu needs to check the srw bit and set its tx/rx mode accordingly. 1 = addressed as a slave 0 = not addressed writing to the m-bus control register clears this bit. mbb bus busy bit this bit indicates the status of the bus. when a start signal is detected, the mbb is set. if a stop signal is detected, it is cleared. 1 = bus busy 0 = bus idle address: $001b bit 7 654321 bit 0 read: mcf maas mbb mal srw mif rxak write: mal clr mif clr reset: 1000001 = unimplemented figure 11-7. m-bus status register (msr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus registers MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required mal arbitration lost bit mal is set by hardware when the arbitration procedure is lost during a master transmission. this bit must be cleared by software. srw r/ w command bit when maas is set, the r/ w command bit of the calling address (sent from master) is latched into the r/ w command bit (srw). checking this bit, the cpu can select the slave transmit/receive mode according to the command of master. 1 = slave transmit, master reading from slave 0 = slave receive, master writing to slave mif m-bus interrupt bit mif is set when an interrupt is pending. this will cause an m-bus interrupt request provided mien is set. this bit is set when one of the following events occurs: C transmission of one byte is completed. the bit is set at the falling edge of the ninth clock. C reception of a calling address which matches its own specific address in slave receive mode. C arbitration is lost. this bit must be cleared by writing a logic 0 to it. rxak receive acknowledge bit if rxak is low, it indicates an acknowledge signal has been received after the completion of an 8-bit data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the ninth clock. 1 = no acknowledge received 0 = acknowledge received rxak is set upon reset. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.6.5 m-bus data i/o register in master transmit mode, data written to this register is sent (msb first) to the bus automatically. in master receive mode, reading from this register initiates reception of the next byte of data. this is accomplished by holding the scl clock line low until a read of this register occurs. once the data is read, the device releases the scl line to allow the transmitting device to transmit the next byte. in slave mode, the same function is available after it is addressed. address: $001c bit 7 654321 bit 0 read: md7 md6 md5 md4 md3 md2 md1 md0 write: reset: unaffected by reset figure 11-8. m-bus data i/o register (mdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface m-bus registers MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required figure 11-9. flowchart of m-bus interrupt routine clear mif master tx/rx last byte to be read last byte transmitted tx rx rxak=0 n write next byte to mdr generate stop signal y n y set txak = 1 n n generate stop signal y read data from mdr and store clear mal y n maas = 1 maas = 1 srw = 1 y tx/rx read mdr and store set tx mode write to mdr set rx mode dummy read from mdr ack from receiver tx next byte switch to rx mode dummy read from mdr arbitration lost last 2nd byte to be read rti n y tx rx n y n n (write) y (read) yn mode f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.7 m-bus pin configuration when the m-bus interface is enabled with the men bit and the mmux bit in the m-bus control register (mcr), the port b data direction register bits 6 and 7 relinquish control to the m-bus control register bits. enabling the m-bus does not alter the state of the port b ddr bits. 11.8 programming considerations programming considerations are discussed in the following subsections. 11.8.1 initialization initialization is accomplished using the following steps: 1. update frequency divider register (mfdr) to select an scl frequency. 2. update m-bus address register (madr) to define its own slave address. 3. set men bit of the m-bus control register (mcr) to enable the m-bus interface system and set the mmux bit to allow m-bus control of the pb7 and pb6 pins. 4. modify the m-bus control register (mcr) bits to select master/slave mode, transmit/receive mode, interrupt enable, or not. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface programming considerations MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required 11.8.2 generation of a start signal and the first byte of data transfer after completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. if the device is connected to a multimaster bus system, the state of the m-bus busy bit (mbb) must be tested to check whether the serial bus is free. if the bus is free (mbb = 0), the start condition and the first byte (the slave address) can be sent. an example of a program which generates the start signal and transmits the first byte of data (slave address) is shown here. (the mmux bit must be set to allow control of pb7 and pb6 pins.) sei ; disable interrupt chfalg brset 5,msr,chflag; check the mbb bit of the ; status register. if it is ; set, wait until it is clear txstart bset 4,mcr ; set transmit mode bset 5,mcr ; set master mode ; i.e., generate start condition lda #calling ; get the calling address sta mdr ; transmit the calling ; address cli ; enable interrupt f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.8.3 software responses after transmission or reception of a byte transmission or reception of a byte will set the data transferring bit (mcf) to a logic 1, which indicates one byte of communication is finished. also, the m-bus interrupt bit (mif) is set to generate an m-bus interrupt if the interrupt function is enabled during initialization. software must clear the mif bit in the interrupt routine first. the mcf bit will be cleared by reading from the m-bus data i/o register (mdr) in receive mode or writing to mdr in transmit mode. software may serve the m-bus i/o in the main program by monitoring the mif bit if the interrupt function is disabled. the following is an example of a software response by a master transmitter in the interrupt routine. see figure 11-9 . isr bclr 1,msr ; clear the mif flag brclr 5,mcr,slave ; check the msta flag, ; branch if slave mode brclr 4,mcr,receive ; check the mode flag, ; branch if in receive mode brset 0,msr,end ; check ack from receiver ; if no ack, end of ; transmission transmit lda databuf ; get the next byte of data sta mdr ; transmit the data f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface programming considerations MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required 11.8.4 generation of the stop signal a data transfer ends with a stop signal generated by the master device. a master transmitter can simply generate a stop signal after all the data has been transmitted. the following is an example showing how a stop condition is generated by a master transmitter. mastx brset 0,msr,end ; if no ack, branch to end lda txcnt ; get value from the ; transmitting counter beq end ; if no more data, branch to ; end lda databuf ; get next byte of data sta mdr ; transmit the data dec txcnt ; decrease the txcnt bra emastx ; exit end bclr 5,mcr ; generate a stop condition emastx rti ; return from interrupt if a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. this can be done by setting the transmit acknowledge bit (txak) before reading the second to the last byte of data. before reading the last byte of data, a stop signal must be generated first. the following is an example showing how a stop signal is generated by a master receiver. masr dec rxcnt beq enmasr ; last byte to be read lda rxcnt deca ; check last 2nd byte to be read bne nxmar ; not last one or last second lamar bset 3,mcr ; last second, disable ack ; transmitting bra nxmar enmasr bclr 5,mcr ; last one, generate 'stop' ; signal nxmar lda mdr ; read data and store sta rxbuf rti f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface 11.8.5 generation of a repeated start signal if at the end of data transfer the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without first generating a stop signal. a program example is shown here. restart bclr 5,mcr ; another start (restart) is bset 5,mcr ; generated by these two ; consequence instruction lda #calling ; get the calling address sta mdr ; transmit the calling ; address 11.8.6 slave mode in the slave service routine, the master addressed as slave bit (maas) should be tested to see if a calling of its own address has just been received. if maas is set, software should set the transmit/receive mode select bit (mtx bit of mcr) according to the r/ w command bit (srw). writing to the mcr clears the maas automatically. a data transfer may then be initiated by writing information to mdr or dummy reading from mdr. in the slave transmitter routine, the received acknowledge bit (rxak) must be tested before transmitting the next byte of data. if rxak is set, indicating an end of the data signal from the master receiver, then rxak must switch from transmitter mode to receiver mode by software. a dummy read must follow to release the scl line so that the master can generate a stop signal. 11.8.7 arbitration lost if more than one master wants to engage the bus simultaneously, only one master wins and the others lose arbitration. the arbitration loss devices immediately switch to slave receive mode by hardware. their data output to the sda line is stopped, but the internal transmitting clock still runs until the end of the current byte transmission. an interrupt occurs when this dummy byte transmission is accomplished with f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola bus (m bus) interface operation during wait mode MC68HC705E5 rev. 1.0 general release specification motorola bus (m bus) interface non-disclosure agreement required mal = 1 and msta = 0. if one master attempts to start transmission while the bus is being engaged by another master: 1. the hardware will inhibit the transmission. 2. the msta bit will switch from one to zero without generating a stop condition. 3. interrupt to cpu will be generated. 4. mal will be set to indicate that the attempt to engage the bus has failed. in consideration of these cases, the slave service routine should test the mal first, and software should clear the mal bit if it is set. 11.9 operation during wait mode during wait mode the m-bus block is idle. if in slave mode, the m-bus block will wake up on receiving a valid start condition. if the interrupt is enabled, the cpu will come out of wait mode after the end of a byte transmission. 11.10 operation during stop mode in stop mode, the whole block is disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required motorola bus (m bus) interface general release specification MC68HC705E5 rev. 1.0 motorola bus (m bus) interface f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required general release specification MC68HC705E5 section 12. synchronous serial interface (ssi) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3 ssi signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.1 serial clock (sck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.3.2 serial data input/output (sdio) . . . . . . . . . . . . . . . . . . . . .98 12.4 ssi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.4.1 ssi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 12.4.2 ssi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.4.3 ssi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 12.5 ssi during stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 12.6 ssi during wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 12.7 ssi pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) 12.2 introduction this synchronous serial i/o module is also used on the mc68hc05x1. the module is similar to the siop used on the mc68hc05p7 and the mc68hc705p9 and the spi used on the mc68hc05l5. the ssi is a two-wire master/slave system including serial clock (sck) and serial data input output (sdio). data is transferred eight bits at a time. an interrupt may be generated at the completion of each transfer, and a software programmable option determines whether the ssi transfers data most significant bit (msb) or least significant bit (lsb) first. when operating as a master device, the serial clock speed is selectable between four rates; as a slave device, the clock speed may be chosen over a wide range. refer to figure 12-1 . in master mode, transmission is initiated by a write to the ssi data register (sdr). a transfer cannot be initiated in slave mode; however, the external master will initiate the transfer. the programmer must choose between master or slave mode before the ssi is enabled. it is up to the programmer to ensure that only one master exists in the system at any one time. all devices in the system must operate with the same clock polarity and data rates. slaves should always be disabled before the master is disabled. likewise, the master should always be enabled before the slaves are enabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) introduction MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required figure 12-1. ssi block diagram interrupt circuit to interrupt logic ssi status register ssi control register ssi data register hff sdio sck clock generator sf dcol start se mstr sr lsbf control logic 00000 se data bus controls/address bus cpol & mstr internal bus pb3/tipl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) 12.3 ssi signals the following sections describe the ssi signals. 12.3.1 serial clock (sck) in master mode (mstr = 1), the sck pin is an output with a selectable frequency of: f op divided by 16 (sr1:sr0 = 00), f op divided by 8 (sr1:sr0 = 01), f op divided by 4 (sr1:sr0 = 10), or f op divided by 2 (sr1:sr0 = 11). this pin will be high (cpol = 1) or low (cpol = 0) between transmissions. in slave mode (mstr = 0), the sck pin is an input and the clock must be supplied by an external master with a maximum frequency of f op divided by 2. there is no minimum sck frequency. this pin should be driven high (cpol = 1) or low (cpol = 0) between transmissions by the external master and must be stable before the ssi is first enabled (se = 1). note: data is always captured with the sdio pin on the rising edge of sck. data is always shifted out and presented at the sdio pin on the falling edge of sck. 12.3.2 serial data input/output (sdio) this pin receives and transmits data to or from the ssi module as described in the following paragraphs. sdio as an output pin prior to enabling the ssi (se = 0), the sdio pin will be three-stated. the sdio pin will be active when the ssi is enabled (se = 1), the serial direction (sdir = 1) bit is set, and mstr = 1. the state of the f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi signals MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required pin will depend on the value of the cpol bit. data can be sent or received in either msb first format (lsbf = 0) or lsb first format (lsbf = 1). if (cpol = 1), the first falling edge of sck will shift the first data bit out to the sdio pin. subsequent falling edges of sck will shift the remaining data bits out. if (cpol = 0), the first data bit will be driven out to the sdio pin before the first rising edge of sck. subsequent falling edges of sck will shift the remaining data bits out. sdio as an input pin the sdio pin will accept data once the ssi is enabled and the sdir bit = 0. valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. see figure 12-2 and figure 12-3 . figure 12-2. synchronous serial interface timing (cpol = 1) figure 12-3. synchronous serial interface timing (cpol = 0) s dio bit 1 bit 2 bit 3 bit 7 sck bit 8 se s dio bit 1 bit 2 bit 3 bit 7 sck bit 8 se f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) 12.4 ssi registers the ssi registers are described in the following subsections. 12.4.1 ssi control register this register is located at address $000a. a reset clears all of these bits, except bit 3 which is set. writes to this register during a transfer should be avoided, with the exception of clearing the se bit to disable the ssi. in addition, the clock polarity, rate, data format, and master/slave selection should not be changed while the ssi is enabled (se = 1) or being enabled. always disable the ssi, by clearing the se bit, before altering control bits within the scr. sie ssi interrupt enable this bit determines whether an interrupt request should be generated when a transfer is complete. reset clears this bit. 1 = an interrupt request will be made if the cpu is in the run or wait mode of operation and the status flag bit sf is set. 0 = no interrupt requests will be made by the ssi. se ssi enable when this bit is set, it enables the ssi and sck pins. when this bit is cleared, any transmission in progress is aborted and the sck and sdio are three-stated. the se bit is readable and writable any time. clearing se while a data transfer is occurring will abort the transmission and reset the bit counter. reset clears this bit. 1 = enable the ssi module. 0 = disable the ssi module. address: $000a bit 7 654321 bit 0 read: sie se lsbf mstr cpol sdir sr1 sr0 write: reset: 00001000 figure 12-4. ssi control register (scr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi registers MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required lsbf least significant bit first the lsbf bit determines the format of the data transfer. the two formats are least significant bit (lsb) or most significant bit (msb) transferred or received first. reset clears this bit, initializing the ssi to msb first order. 1 = data will be sent and received in an lsb first format. 0 = data will be sent and received in an msb first format. mstr master mode reset clears this bit and configures the ssi for slave operation. mstr may be set at any time regardless of the state of se. 1 = ssi is configured for master mode. the transmission is initiated by a write to the data register and the sck pin becomes an output providing a synchronous data clock at a rate determined by the sr bit. 0 = ssi is configured to slave mode. any transmission in progress is aborted. transfers are initiated by an external master which should supply the clock signal to the sck pin. cpol clock polarity the clock polarity bit controls the state of the sck pin between transmissions. 1 = sck will be high between transmissions. 0 = sck will be low between transmissions. in both cases, the data is latched on the rising edge of sck for serial input and is valid on the rising edge of sck for serial output. reset sets this bit. sdir serial data direction when the se bit = 1, sdir functions as the output driver enable bit for the sdio pin with ssi in master or in slave mode. this bit has no effect on the sdio pin when the ssi is disabled (se = 0). this bit is cleared by reset. 1 = enable the output driver of the sdio pin. 0 = disable the output driver of the sdio pin. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) sr1 and sr0 ssi clock rate select these bits determine the frequency of sck when in master mode (mstr = 1). they have no effect in slave mode (mstr = 0). table 12-1. master mode sck frequency select sr1 sr0 sck frequency 00 f op ? 16 01 f op ? 8 10 f op ? 4 11 f op ? 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi registers MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required 12.4.2 ssi status register the ssi status register (ssr) is located at address $000b and contains three bits. sf ssi flag this bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. it has no effect on any further transmissions and can be ignored without problem. however, sf must be cleared before a master can initiate a transfer. sf is cleared by reading the ssr with sf set followed by a read or write of the serial data register. if it is cleared before the last edge of the next byte, it will be set again. reset clears this bit. dcol data collision this is a read-only status bit which indicates that an invalid access to the data register has been made. this can occur any time after the first falling edge of sck and before sf is set. dcol is cleared by reading the status register with sf set followed by a read or write of the data register. if the last part of the clearing sequence is done after another transmission has been started, dcol will be set again. reset also clears this bit. tipl the state of the pb3 pin is latched and placed into this bit on the eighth rising sck clock during a shift operation. this is the case regardless of the state of mstr and cpol in the ssi control register. reset clears this bit. address: $000b bit 7 654321 bit 0 read: sf dcol 00000 tipl write: reset: 00001000 = unimplemened figure 12-5. ssi status register (ssr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) 12.4.3 ssi data register this register is located at address $000c and is both the transmit and receive data register. this system is not double buffered but writes to this register during transfers are masked and will not destroy the previous contents. the sdr can be read at any time but if a transfer is in progress the results may be ambiguous. this register should only be written to when the ssi is enabled (se = 1). 12.5 ssi during stop mode in stop mode, the ssi halts operation. the sdio and sck pins will maintain their states. if the ssi was nearing completion of a transfer when stop mode is entered, it might be possible for the ssi to generate an interrupt request and cause the processor to immediately exit stop mode. to prevent this occurrence, the programmer should ensure that all transfers are complete before entering stop mode. if the ssi is configured to slave mode, then further care should be taken in entering stop mode. in slave mode, the sck pin will still accept a clock from an external master, allowing potentially unwanted transfers to take place and power consumption to be increased. note that the ssi will not generate interrupt requests in this situation. however, on exiting stop mode through some other means, the sf flag may be found to be set. if, at this point, sie is also set, an interrupt request will be generated. note: to avoid these potential problems, it is safer to disable the ssi completely (se = 0) before entering stop mode. address: $000c bit 7 654321 bit 0 read: write: reset: reset results unknown figure 12-6. ssi data register (sdr) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . synchronous serial interface (ssi) ssi during wait mode MC68HC705E5 rev. 1.0 general release specification synchronous serial interface (ssi) non-disclosure agreement required 12.6 ssi during wait mode the cpu clock halts during wait mode, but the ssi remains active. if interrupts are enabled, an ssi interrupt will cause the processor to exit wait mode. 12.7 ssi pin configuration when the ssi is enabled via the se bit of the scr ($0a), the port b data direction register bits 3C5 relinquish control to the ssi as directed by the combination of the se, mstr, and sdir bits. the states of the port b ddr bits are not altered by the ssi. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required synchronous serial interface (ssi) general release specification MC68HC705E5 rev. 1.0 synchronous serial interface (ssi) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification user eprom non-disclosure agreement required general release specification MC68HC705E5 section 13. user eprom 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3 bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.4 programming register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 13.5 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 13.2 introduction the user eprom consists of 5120 bytes of eprom from $0b00 to $1eff and 16 bytes of user vectors from $1ff0 to $1fff. the bootloader rom and vectors are located from $1f01 to $1fef. all of the user vectors, $1ff2 through $1fff, are dedicated to reset and interrupt vectors. location $1f00 is the mask option register (mor). 13.3 bootloader mode bootloader mode is entered upon the rising edge of reset if the irq is at v tst and the pb1 pin is at logic 1. the bootloader code resides in the rom from $1f01 to $1fef. this program handles copying of user code from an external eprom into the on-chip eprom. the bootload function does not have to be done from an external eprom, but it may be done from a host. the user code must be a one-to-one correspondence with the internal eprom addresses. note: the mcu designer must disable the cop hardware in bootloader mode. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required user eprom general release specification MC68HC705E5 rev. 1.0 user eprom three pins are used to select various bootloader functions: pb0, pb3, and pb4. pb0 is normally a sync pin, which is used to synchronize the mcu to an off-chip source driving eprom data into the mcu. if an external eprom is used, this pin must be connected to v ss . pb4 and pb3 are used to select a programming mode. two other pins, pc2 and pc3, are used to drive the prog led and the verf led, respectively. the programming modes along with gate and drain stress are shown in table 13-1 . the bootloader uses an external 12-bit counter to address the memory device containing the code to be copied. this counter requires a clock and a reset function. the 12-bit counter can address up to 4 kbytes of memory, which means that a port pin has to be used to address the extra memory space. table 13-1. bootloader functions pb0 pb4 pb3 mode sync 1 1 program/verify sync 1 0 verify only sync 0 0 factory test 0 0 1 factory test 1 0 1 factory test f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . user eprom bootloader mode MC68HC705E5 rev. 1.0 general release specification user eprom non-disclosure agreement required figure 13-1. programmer interface to host data out port a clk (out) sync (in) host read data (a) dump eprom interface to a host clk (out) sync (in) data in (b) program/verify interface to a host data read f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required user eprom general release specification MC68HC705E5 rev. 1.0 user eprom figure 13-2. MC68HC705E5 bootloader flowchart boot pb2 = 0 jump to ram put ramsub in ram ddrc <-%00001111 portc <-%00001111 get byte from port a program byte jsr nxtadr gate stress drain stress ddra = output get byte start @ $b00 put byte on port a change instruction from sta to eor inc count to $b00 start addr <- $b00 get byte from port a jsr ramsub jsr nxtadr end address ($1fff) end address ($1fff) wait wait pb0=1 (sync) wait verf led on compare end addr ($1fff) pb4 = 1 pb3 = 1 pb4 = 1 pb0 = 1 yes yes no yes no yes yes yes yes yes yes no no no no no no no no yes dump eprom prg/verf verify mayprg bump count to $b00 bump count to $b00 ddrb <-%00100000 portb <-%00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . user eprom bootloader mode MC68HC705E5 rev. 1.0 general release specification user eprom non-disclosure agreement required figure 13-3. MC68HC705E5 programming circuit v dd a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 clk rst pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 mc14040b d0 d1 d2 d3 d4 d5 d6 d7 osc1 osc2 reset pb0 (sync) pc2 pc3 pc1 pc0 irq/v pp prog verf 2764 ce oe pb5 pb3 pb4 pb2 v dd v dd v dd v dd v pp 15 pf 10 mw 10.24 mhz 15 pf 10 9 8 7 6 5 4 3 25 24 21 23 2 9 7 6 5 3 2 4 13 12 14 15 1 11 10 11 12 13 15 16 17 18 19 20 22 all resistors are 10 k w unless specified otherwise. 390 w 390 w v d d 16 8 v ss v dd 14 28 27 1 v dd pb1 v dd pd5 mc74hc02 2 3 5 6 8 9 11 13 10 4 1 14 7 v dd 12 v ss2 v dd2 v dd2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required user eprom general release specification MC68HC705E5 rev. 1.0 user eprom 13.4 programming register this register is used to program the eprom array. only the latch and epgm bits are available in user mode. to program a byte of eprom, set latch, write data to the desired address, then set epgm for t epgm . latch eprom latch control read: any time write: any time 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming. causes address and data bus to be latched when a write to eprom is done. eprom cannot be read if latch = 1. epgm eprom program control read: any time write: cleared any time, set only if latch = 1 0 = programming power switched off the eprom array 1 = programming power switched on to the eprom array. if latch = 0, then epgm is cleared automatically. epgm cannot be set if latch is not set. latch and epgm cannot both be set on the same write. address: $0011 bit 7 654321 bit 0 read: latch0 epgm write: reset: 00001000 figure 13-4. programming register (prog) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . user eprom mask option register MC68HC705E5 rev. 1.0 general release specification user eprom non-disclosure agreement required 13.5 mask option register the mor contains programmable eprom bits to control mask options. the mor register is latched upon reset going away. stopen stop enable when set, stop is enabled. cpi1, cpi0 cpi rate bits read: any time write: in special modes, writing these bits activates the function without having to program it and can be written many times. in user mode, writing has no effect. these bits must be programmed. refer to table 13-2 . irq irq sensitivity 1 = this bit selects the edge and level sensitive irq. 0 = this bit selects the edge-only sensitive irq (eprom erased state). address: $1f00 bit 7 654321 bit 0 read: stopen cpi1 cpi0 irq cop write:: reset: 00001000 figure 13-5. mask option register (mor) table 13-2. cpi rate cpi1 cpi0 interrupt rate 0 x 1 second cpi rate 1 0 0.5 second cpi rate 1 1 0.25 second cpi rate f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required user eprom general release specification MC68HC705E5 rev. 1.0 user eprom in test mode, reading and writing the mor is done according to table 13-3 . cop cop enable when set, this bit enables the cop watchdog timer. when clear, the cop is disabled. 1 = the cop is enabled. 0 = the cop is disabled (eprom erased state). table 13-3. mor read/write based on mode and latch bit latch test read write 00en pe = program eprom byte r = register latch n = nothing e = eprom byte 10npe 01er 11rpe f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required general release specification MC68HC705E5 section 14. instruction set 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.3 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 14.3.1 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.2 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.3 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.4 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 14.3.5 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.6 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.7 indexed,16-bit offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 14.3.8 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 14.4 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 14.4.1 register/memory instructions . . . . . . . . . . . . . . . . . . . . . .120 14.4.2 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . .121 14.4.3 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . .122 14.4.4 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . .124 14.4.5 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 14.5 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.2 introduction the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. 14.3 addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set addressing modes MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required 14.3.1 inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. 14.3.2 immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 14.3.3 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. 14.3.4 extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.3.5 indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. 14.3.6 indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 14.3.7 indexed,16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required 14.3.8 relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 14.4 instruction types the mcu instructions fall into the following five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.4.1 register/memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 14-1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required 14.4.2 read-modify-write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. table 14-2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.4.3 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required table 14-3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.4.4 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. table 14-4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction types MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required 14.4.5 control instructions these instructions act on cpu registers and control cpu operation during program execution. table 14-5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set 14.5 instruction set summary table 14-6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 c b0 b7 0 b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 table 14-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (a) x ? ( x) = $ff C (x) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 table 14-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 table 14-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 c b0 b7 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required instruction set general release specification MC68HC705E5 rev. 1.0 instruction set ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 table 14-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc b0 b7 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . instruction set instruction set summary MC68HC705E5 rev. 1.0 general release specification instruction set non-disclosure agreement required tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?ag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?ag z zero ?ag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?ag set or cleared n any bit not affected table 14-6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required general release specification MC68HC705E5 rev. 1.0 instruction set instruction set table 14-7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification electrical specifications non-disclosure agreement required general release specification MC68HC705E5 section 15. electrical specifications 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 15.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 15.4 operating temperature range. . . . . . . . . . . . . . . . . . . . . . . .135 15.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 15.6 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . .136 15.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 15.8 m-bus interface input signal timing. . . . . . . . . . . . . . . . . . . .140 15.9 m-bus interface output signal timing . . . . . . . . . . . . . . . . . .140 15.2 introduction this section contains the electrical and timing specifications. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical speci?cations general release specification MC68HC705E5 rev. 1.0 electrical specifications 15.3 maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 15.6 dc electrical characteristics for guaranteed operating conditions. rating symbol value unit supply voltage v dd C0.3 to +7.0 v input voltage v in v ss C0.3 to v dd +0.3 v bootloader mode ( irq pin only) v in v ss C0.3 to 2x v dd +0.3 v current drain per pin excluding v dd and v ss i25ma storage temperature range t stg C65 to +150 c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications operating temperature range MC68HC705E5 rev. 1.0 general release specification electrical specifications non-disclosure agreement required 15.4 operating temperature range 15.5 thermal characteristics characteristic symbol value unit operating temperature range mc68hc(7)05e5dw (standard) mc68hc(7)05e5p t a t l to t h 0 to +70 0 to +70 c characteristic symbol value unit thermal resistance plastic dip soic q ja 60 60 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p d x(t a + 273 c ) + p d 2 x q ja w/ c average junction temperature t j t a + (p d x q ja ) c maximum junction temperature t jm 125 c notes: 1. power dissipation is a function of temperature. 2. k is a constant unique to the device. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical speci?cations general release specification MC68HC705E5 rev. 1.0 electrical specifications 15.6 dc electrical characteristics characteristic symbol min typ max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C0.1 0.1 v output high voltage (i load C0.8 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v oh v dd C0.8 v output low voltage (i load = 1.6 ma) pa0Cpa7, pb0Cpb7, pc0Cpc3 v ol 0.4 v input high voltage pa0Cpa7, pb0Cpb7, pc0Cpc3, irq, reset, osc1 v ih 0.7xv dd v dd v input low voltage pa0Cpa7, pb0Cpb7, pc0Cpc3, irq, reset, osc1 v il v ss 0.3 x v dd v eprom programming voltage v in 14.5 15.5 v xfc wide bandwidth source sink i oh i ol C50 50 C100 100 m a xfc narrow bandwidth source sink i oh i ol C1 1 C2 2 m a supply current (see notes) run (f osc = 32.768 khz, f op = 16.384 khz) (f osc = 4.2 mhz, f op = 2.1 mhz) wait (f osc = 32.768 khz, f op = 16.384 khz) (f osc = 4.2 mhz, f op = 2.1 mhz) stop (pll off) 25 o c i dd 120 2.5 50 0.7 10 400 3.5 150 1 50 m a ma m a ma m a i/o ports hi-z leakage current pa0Cpa7, pb0Cpb7, pc0Cpc3 i oz 10 m a input current reset, irq, osc1 i in 1 m a capacitance ports as input or output reset, irq c out c int 12 8 pf notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 c to +70 c, unless otherwise noted 2. typical values at midpoint of voltage range, 25 c only 3. wait i dd : only timer and cpi systems active 4. run (operating) i dd , wait i dd : measured using external square wave clock source; all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 5. wait, stop i dd : all ports con?gured as inputs; v il = 0.2; v ih = v dd C0.2 v 6. stop i dd measured with osc1 = v ss 7. wait i dd affected linearly by the osc2 capacitance f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications dc electrical characteristics MC68HC705E5 rev. 1.0 general release specification electrical specifications non-disclosure agreement required figure 15-1. maximum supply current versus operating frequency figure 15-2. typical supply current versus operating frequency run i dd 0 1.0 2.0 2.5 3.5 0.277 1.319 0.798 1.058 v dd = 5.0 v t a = C0 c to 70 c supply current (ma) 0.016 1.840 operating frequency (mhz) 1.579 0.5 1.5 3.0 0.537 2.100 wait i dd run i dd 0 1.0 2.0 2.5 0.277 1.319 0.798 1.058 v dd = 5.0 v t a = C0 c to 70 c supply current (ma) 0.016 1.840 operating frequency (mhz) 1.579 0.5 1.5 0.537 2.100 wait i dd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical speci?cations general release specification MC68HC705E5 rev. 1.0 electrical specifications 15.7 control timing figure 15-3. external interrupt mode diagram characteristic symbol min max unit frequency of operation crystal option external clock option f osc dc 32.768 4.2 khz mhz internal operating frequency crystal (f osc ? 2) external clock (f osc ? 2) f op dc 16.384 2.1 khz mhz cycle time t cyc 480 ns eprom byte programming time t epgm 10ms reset pulse width t rl 1.5 t cyc interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil see note 2 t cyc osc1 pulse width t oh ,t ol 90 ns pll startup stabilization time t plls 50 ms notes: 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = 0 o c to +70 o c, unless otherwise noted 2. the minimum period, t ili , should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 t cyc . irq t ilih t ilih t ilih irq1 irqn irq (mcu) normally used with wire-ored connection . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification electrical specifications electrical specifications control timing non-disclosure agreement required figure 15-4. power-on reset and reset pch pcl osc1 2 reset internal processor internal address bus 1 1ffe 1fff v dd v dd threshold (1 to 2 v typical) t vddr 4064 t cyc t cyc t rl internal data bus 1 1ffe 1ffe 1ffe 1ffe new pc 1fff notes: 1. internal timing signal and bus information are not available externally. 2. osc1 line is not meant to represent frequency. it is only used to represent time. 3. the next rising edge of the internal processor clock following the rising edge of reset initiates the reset sequence. 3 new new op code pcl pch new pc new pc op code new pc clock 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical speci?cations general release specification MC68HC705E5 rev. 1.0 electrical specifications 15.8 m-bus interface input signal timing 15.9 m-bus interface output signal timing characteristic symbol min max unit start condition hold time t hd.sta 2t cyc clock low period t l ow 4.7 t cyc clock high period t h igh 4t cyc sda/scl rise time t r 1.0 ms sda/scl fall time t f 300 ns data setup time t su.dat 250 ns data hold time t hd.dat 0t cyc start condition setup time (for repeated start condition only) t su.sta 2t cyc stop condition setup time t su.sto 2t cyc note: v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 o c to +85 o c, unless otherwise noted characteristic symbol min max unit start condition hold time t hd.sta 12 t cyc clock low period t l ow 11 t cyc clock high period t h igh 11 t cyc sda/scl rise time t r 1.0 ms sda/scl fall time t f 300 ns data setup time t su.dat t low Ct cyc ns data hold time t hd.dat 0t cyc start condition setup time (for repeated start condition only) t su.sta 10 t cyc stop condition setup time t su.sto 12 t cyc note: v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = C40 o c to +85 o c, unless otherwise noted f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . electrical specifications m-bus interface output signal timing MC68HC705E5 rev. 1.0 general release specification electrical specifications non-disclosure agreement required figure 15-5. m-bus interface timing t hd.sta t hd.dat t su.sto sda scl t low t su.dat t high f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required electrical speci?cations general release specification MC68HC705E5 rev. 1.0 electrical specifications f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification mechanical data non-disclosure agreement required general release specification MC68HC705E5 section 16. mechanical data 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 16.3 28-pin plastic dual-in-line package (case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 16.4 28-pin small outline integrated circuit package (case 751f-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 16.2 introduction this section describes the dimensions of the plastic dual in-line package (pdip) and small outline integrated circuit (soic) mcu packages. 16.3 28-pin plastic dual-in-line package (case 710-02) ! ! ! #! %% ! $" ! ! ! ! ! ! ! ! # ! " 114 15 28 b a c n k m j d f hg l f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required mechanical data general release specification MC68HC705E5 rev. 1.0 mechanical data 16.4 28-pin small outline integrated circuit package (case 751f-04) ! ! % ! ! ! " ! " $" ! " ! " ! " # ! " ! ! $ ! $" ! ! -a- -b- 114 15 28 -t- c m j -t- k 26x g 28x d 14x p r x 45 ? ! f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC705E5 rev. 1.0 general release specification ordering information non-disclosure agreement required general release specification MC68HC705E5 section 17. ordering information 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 17.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 17.2 introduction this section contains ordering information. 17.3 mc order numbers table 17-1 shows the mc order numbers for the available package types. table 17-1. mc order numbers package type operating temperature range mc order number 28-pin plastic dual in-line package (pdip) 0 c to 70? c MC68HC705E5p 28-pin small outline integrated circuit package (soic) 0 c to 70? c MC68HC705E5dw f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . non-disclosure agreement required ordering information general release specification MC68HC705E5 rev. 1.0 ordering information f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ? motorola, inc., 1997 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
Price & Availability of MC68HC705E5
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